TimingDesigner* (i960 supported)

TimingDesigner* is software for accurately modeling, visualizing, analyzing and documenting digital circuit timing. TimingDesigner is used with any type of Intel design - chip, board or system - where timing is important, or where accurate timing and interface specifications must be communicated to others. TimingDesigner models complex digital circuit timing by combining an interactive timing diagram editor with a special-purpose timing spreadsheet.
The engineer first creates a timing diagram with the timing diagram editor, which shows the waveforms (sequence of events), delays (cause-and-effect relationships) and timing constraints of a proposed design.
The spreadsheet is then used to enter the min/max values of each delay and constraint. These values may be complex formulas - including min/max variables - so that path delays, different rise/fall times, loading, temperature and other effects can be accurately modeled. After each modification, TimingDesigner's static timing engine traces all of the delay paths specified in the timing diagram, removes common delays, adjusts for delays which track, selects the critical paths and then computes the worst-case timing margins by comparing the total delay along each critical path to the minimum or maximum allowable value specified in each constraint.